1. Field of the Invention
The invention relates to semiconductor devices with wells formed in a semiconductor substrate and having different impurity concentration profiles.
The invention further relates to a manufacturing method for forming wells having different impurity concentration profiles in a semiconductor substrate.
2. Description of the Background Art
FIG. 3 is a structural cross-sectional view showing a well structure used in a conventional semiconductor memory device. A p-well 2 and an n-well 3 of different conductivity types are formed on the surface region of a p-type silicon substrate 1. A field oxide 8 for isolation is formed in predetermined regions on the surface of each of the well regions 2, 3. A channel stopper 26 is formed under the field oxide 8. The well shown in FIG. 3 has a so-called diffusion-type well structure formed using a thermal diffusion process. An MOS transistor 6 is formed on the surface of the p-well region 2 and a p MOS transistor 7 is formed on the surface of the n-well region 3. While only one transistor is shown in the drawing, this is only by way of example and, actually, a plurality of transistors and other functional devices are formed. The n MOS transistor 6 has a gate electrode 27 and a pair of n-type source-drain regions 25, 25. The p MOS transistor 7 has a gate electrode 27 and a pair of p-type source-drain regions 24, 24.
A manufacturing method of the well structure shown in FIG. 3 will now be described. FIGS. 4A to 4F are cross-sectional views of a manufacturing process of the well structure in FIG. 3. Firstly, as shown in FIG. 4A, a nitride film 10 and a resist 11a are deposited on the surface of the p-type silicon substrate 1, and then patterned to a predetermined configuration. An n-type impurity ions 15 such as phosphorus (P) are implanted on the surface of the silicon substrate 1 with the patterned resist 11a as a mask.
Then, as shown in FIG. 4B, a thick LOCOS (Local Oxidation of Silicon) oxide film 9 is formed on the surface of the n well region by a thermal oxidation method using the nitride film 10 as a mask.
Furthermore, as shown in FIG. 4C, after covering the surface of the LOCOS oxide film 9 with a resist 11b, a p-type impurity ions 16 such as boron (B) are implanted on the surface of the silicon substrate 1 with the resist 11b as a mask.
Then, as shown in FIG. 4D, an n-well and a p-well regions 3, 2 are formed by applying a several hours of thermal treatment at 1100.degree. C. to 1200.degree. C. and thermally diffusing the impurity. After that, LOCOS oxide film 9 is removed.
Furthermore, as shown in FIG. 4E, after forming the nitride film 10 and the resist 11c on the surface of the silicon substrate 1, patterning is effected and only a region where a field oxide should be formed is apertured. Then a resist pattern is newly formed only in the region to be an n-well and, using this as a mask, an impurity ions 17 of the same conductivity type as that of the well region 2 are supplied on the surface of the silicon substrate 1.
After that, as shown in FIG. 4F, a thermal oxidation treatment with the nitride film 10 as a mask is applied and a field oxide 8 and a channel stopper 26 are formed.
The above-mentioned diffusion-type well structure has, however, a disadvantage that a so-called narrow channel effect is caused. FIG. 5 is a structural plan view prepared for describing the narrow channel effect. Referring to FIGS. 3 and 5, a p.sup.30 channel stopper 26 of a higher concentration than that of p-well region is formed under the field oxide 8. The channel stopper 26 diffuses from the region under the field oxide to the channel region of a MOS transistor 6 by the effect of the heat applied on the substrate in a process for forming the MOS transistor 6 on the surface of the p-well region 2. The gate width W of the MOS transistor 6 is therefore decreased. The concentration of the substrate is effectively increased in terms of an average effect. Such a narrow channel effect decreases the drive current of the transistor or increases the threshold voltage. FIG. 6 is a diagram showing the relationship between the channel width and the threshold voltage of the transistor. As shown in the drawing, it can be seen that the MOS transistor formed in the diffusion-type well region has the threshold voltage V.sub.TH suddenly raised when the channel width becomes 0.8 .mu.m or below.
There is a tendency that it is difficult to set the threshold voltage V.sub.TH of a MOS transistor formed on the surface to a low level in a diffusion-type well structure. FIG. 7 is an impurity concentration profile diagram showing an impurity concentration profile of the substrate depth direction of a well formed by a diffusion method. The diagram shows a profile in which the impurity concentration changes smoothly with respect to the substrate depth direction from the surface of the substrate. In this case, when channel doping is effected in the vicinity of the surface of the substrate, the concentration of the substrate is increased and the threshold voltage V.sub.TH of a transistor formed on the surface is increased. When the threshold voltage V.sub.TH is increased, the drive current of the transistor is decreased. When a high concentration region of the impurity is formed on the surface of the substrate, impurity scattering becomes ready to occur on this surface, and furthermore the junction capacitance of the source-drain and the substrate is increased, so that the drive current of the transistor is decreased.
A retrograde well structure is proposed as a structure for overcoming the above-mentioned disadvantage of a diffusion-type well structure. FIG. 8 is a structural cross-sectional view showing this retrograde well structure. That is, a p-well region 2 and an n-well region 3 formed on the surface of a p-type silicon substrate 1 respectively have predetermined concentration profiles which were set using a high-energy ion implantation method, respectively. A manufacturing process of this retrograde well structure will be described in the following.
FIGS. 9A to 9C are cross-sectional views of a manufacturing process of a retrograde well structure. Firstly, as shown in FIG. 9A, field oxides 8a, 8b are formed in predetermined positions on the surface of the silicon substrate 1 using the LOCOS method. After that, a resist pattern 11a is coated on a region where a p-well region 2 should be formed. Then, an n-type impurity ions 16 such as phosphorus are implanted with a predetermined implantation energy to form a first impurity concentration region 3c at a deep position in the silicon substrate 1.
Next, as shown in FIG. 9B, the second ion implantation is conducted to form a second impurity concentration regions 3b such that a high concentration region may be located under the field oxides 8a, 8b.
Furthermore, as shown in FIG. 9C, the third ion implantation is conducted to form a third impurity concentration region 3c of a predetermined concentration on the substrate surface. An n-well region 3 having a predetermined impurity concentration profile is formed by the above-mentioned ion-implantation process. A p-well region 2 is also formed using a method similar to the above-mentioned.
An impurity concentration profile of the retrograde well region formed by the above-mentioned processes is shown in FIG. 10. Referring to FIG. 10, this retrograde well structure is characterized in that impurity concentration regions each having a predetermined function can be formed in the direction of the substrate depth of the well region. That is, the first impurity concentration region 3a formed at the deep position of the substrate is effective for preventing a so-called latch up phenomenon. The second impurity concentration region 3b located at the intermediate depth functions as a channel stop region for isolation. The third impurity concentration region 3c formed near the surface of the substrate controls the occurrence of a punch through phenomenon or controls the threshold voltage V.sub.TH of the transistor.
In this way, in accordance with a well structure having an optimized concentration profile, it is possible to overcome a problem such as a narrow channel effect as caused in the above-mentioned diffusion-type well or an increase of the threshold voltage.
When it was intended to employ this retrograde well structure over the overall surface of the substrate, however, a new problem as in the following arose. That is, in a semiconductor integrated circuit device formed on one chip, different functions are sometimes required for structural devices in circuits of each kind. For example, in a DRAM, it is necessary to miniaturize the structures of devices such as transistors and enhance integration in a memory cell portion to be a memory region. For this reason, the transistor structure is miniaturized and the isolation region is similarly miniaturized. Conversely, there is relatively less need for miniaturizing or integrating in the peripheral circuits, and rather much importance is attached to a high speed responsibility of the devices. The structures of the transistors are therefore adapted to ensure a comparatively large channel width. Therefore, the arrangement has more space left compared with that of the memory cell and a relatively wide area is occupied by the isolation region. As stated above, a thermal oxide film formed by the LOCOS method is used as an insulating film for isolation. This thermal oxide film has the thickness changed in accordance with the width of the oxide film extending on the surface of the substrate (hereinafter referred to as isolation width). This state is shown in FIGS. 11A and 11B. FIG. 11B is a typical diagram for describing the relationship between the isolation width and the thickness of a field isolation film 8 formed by the LOCOS method. In FIG. 11B (a), the opening width of a nitride film 10 patterned on the surface of the silicon substrate 1 defines the isolation width of the field isolation film. A thermal oxidation treatment is applied to the surface of the silicon substrate 1 using this nitride film 1 as a mask. A field isolation film 8 is thereby formed with a thickness t as shown in FIG. 11B (b). The width of this field isolation film 8 is formed to be wider than the above-mentioned isolation width by the area where a so-called bird's beak is formed. FIG. 11A shows the relationship between the above-mentioned isolation width and the thickness t of the oxide film to be formed. As seen from this diagram, there is a relationship that as the isolation width is decreased, the thickness thereof t is also decreased. Referring back to FIG. 8, the isolation width of the field isolation film 8b is relatively narrow when it is formed in a memory cell array, and the isolation width of the field isolation film 8a is formed to be relatively wide when it is formed in the peripheral circuits. Therefore, the both thicknesses of the field oxides are made different from each other. The difference of the thickness between the field isolation films 8a, 8b causes a disadvantage. That is, referring to FIG. 9B, the second impurity concentration region 3b is formed such that it comes in contact with the lower surfaces of the field isolation films 8a, 8b by the second ion-implantation. If the ion-implantation energy is set such that the second impurity concentration region 3b may be formed under the thick field isolation film 8a, however, this second impurity concentration region 3b is formed at a deeper position than the portion under the thin field isolation film 8b, and it does not function as a channel stopper anymore. Conversely, if the second ion-implantation energy is optimized for the thin field isolation film 8b, there occurs a disadvantage that no channel stopper is formed under the thick field isolation film 8a.